An interconnect circuit board or package is the physical realization of electronic circuits or subsystems from a number of extremely small circuit elements electrically and mechanically interconnected. It is frequently desirable to combine these diverse type electronic components in an arrangement so that they can be physically isolated and mounted adjacent to one another in a single compact package and electrically connected to each other and/or to common connections extending from the package.
Complex electronic circuits generally require that the circuit be constructed of several levels of conductors separated by corresponding insulating dielectric tape layers. The conductor layers are interconnected through the dielectric layers that separate them by electrically conductive pathways, called via fills.
The use of a ceramic-based green tape to make low temperature co-fired ceramic (LTCC) multilayer circuits was disclosed in U.S. Pat. No. 4,654,095 to Steinberg. The co-fired, free sintering process offered many advantages over previous technologies. However, when larger circuits were needed, the firing shrinkage proved too broad to meet the needs. Given the reduced sizes of the current generation of surface mount components, the shrinkage tolerance (reproducibility of shrinkage) has proved too great to permit the useful manufacture of LTCC laminates much larger than 6″ by 6″. This upper limit continues to be challenged today by the need for greater circuit density as each generation of new circuits and packages evolves. In turn this translates into ever-smaller component sizes and thereby into smaller geometry's including narrower conductor lines and spaces and smaller vias on finer pitches in the tape. All of this requires a much lower shrinkage tolerance than could be provided practically by the free sintering of LTCC laminates.
A method for reducing X-Y shrinkage during firing of green ceramic bodies in which a release layer, which becomes porous during firing, is placed upon the ceramic body and the assemblage is fired while maintaining pressure on the assemblage normal to the body surface was disclosed in U.S. Pat. No. 5,085,720 to Mikeska. This method used to make LTCC multilayer circuits provided a significant advantage over Steinberg, as a reduction X-Y shrinkage was obtained through the pressure assisted method.
An improved co-fired LTCC process was developed and is disclosed in U.S. Pat. No. 5,254,191 to Mikeska. This process, referred to as PLAS, an acronym for pressure-less assisted sintering, placed a ceramic-based release tape layer on the two major external surfaces of a green LTCC laminate. The release tape controls shrinkage during the firing process. Since it allows the fired dimension of circuit features to be more predictable, the process represents a great improvement in the fired shrinkage tolerance. During the release tape-based constrained sintering process, the release tape acts to pin and restrain any possible shrinkage in x- and y-directions. The release tape itself does not sinter to any appreciable degree and is removed prior to any subsequent circuit manufacturing operation.
In a more recent invention, U.S. patent application 60/385,697, the teachings of constrained sintering are extended to include the use of a non-fugitive, non-removable, non-sacrificial or non-release, internal self-constraining tape. The fired laminate comprises layers of a primary dielectric tape which define the bulk properties of the final ceramic body and one or more layers of a secondary or self-constraining tape. The sole purpose of the latter is to constrain the sintering of the primary tape so that the net shrinkage in the x,y direction is zero. This process is referred to as a self-constraining process and the acronym SCPLAS is applied. The shrinkage tolerances achieved by this process are very similar to those achieved by the release-tape based constrained sintering process. The self-constraining tape is placed in strategic locations within the structure and remains part of the structure after co-firing is completed. There is no restriction on the placement of the self-constraining tape other than that z-axis symmetry is preserved.
Therefore, symmetrical-only arrangements were available to the circuit designer which has proved to be a significant limitation to the capabilities of LTCC technology. It restricts the designer's freedom to provide the optimal circuit configuration both from the viewpoint of performance, cost and form factor. The current invention with its asymmetical arrangement removes this limitation. It allows the circuit designer a greater flexibility to use the optimal number of tape layers, the most compatible companion conductor, resistor and dielectric materials in achieving the highest-quality circuit function.